High-Performance Vitis HLS Design with Task-Level Parallelism

Summary

The complexity of the algorithms used in today’s AI, wireless, video/image processing, medical, defense, and consumer domains has increased considerably. Vitis^TM High-Level Synthesis (HLS) accelerates IP creation in such domains by synthesizing C/C++ code into RTL code for the programmable logic on select AMD devices. Coding in C/C++ provides a higher level of abstraction, which can mean easier design/algorithm exploration, fewer lines of code to describe the algorithm, faster implementation, easier design re-use and portability, and reduced verification time by orders of magnitude.

Generic C/C++ is executed on a CPU and is therefore highly sequential by nature. However, code intended for execution on an FPGA must be architected in a highly parallel manner so that the tool can infer and exploit the parallelism. A key concept of designing C/C++ for FPGAs is the notion of task level parallelism (TLP). Join us for this webinar in which we will present and discuss:

• Overview and Introduction of Vitis HLS
• Discuss the two key paradigms for implementing TLP.
• Discuss the various channels used to pass data in a TLP region.
• Illustrate these concepts with examples.

Whether you are currently using Vitis HLS or wondering if Vitis HLS is the right choice for your next design project, this webinar will highlight a few key concepts that will help you achieve your FPGA design goals faster.

Featured Speakers

Nicholas Moellers

Product Marketing Manager, Vitis HLS, AMD

Sriranjani Ramasubramanian

Product Marketing Manager, Vitis and Vitis HLS, AMD