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Artix UltraScale+: Serial Throughput Meets Signal Compute Density in a Secure Cost-Optimized FPGA

Webinar

August 5, 2021 | 7:00AM PDT

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Summary


For many, Artix® is synonymous with best-in-class transceivers in a low-power, low-cost solution. As cost-sensitive applications evolve, the demand for higher serial throughput and signal processing power increases. Enter the Artix UltraScale+ FPGA family, the same great Artix, but with UltraScale+ enhancements. With 16Gb/s transceivers for advanced protocols, best-in-class DSP bandwidth in small form-factor packaging, and UltraScale+ grade multi-level security, Artix UltraScale+ exceeds the requirements of cost-sensitive applications across multiple markets.

In this webinar, we’ll give you an overview of the Artix UltraScale+ FPGA family, what we built it for, what it’s capable of, and how it beats similar low-cost solutions where it matters the most. We’ll also walk you through the easiest way to start developing on Artix UltraScale+ FPGAs, utilizing the industry-leading Vivado Design Suite and AU25P Evaluation kit from Opal Kelly.  We’ll highlight the kits rapid prototyping capability with the SYZYGY Ecosystem and Opal Kelly FrontPanel SDK to accelerate your design.


Featured Speakers


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Jayson Bethurem

Product Line Manager, Cost-Optimized Portfolio, Xilinx

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Jake Janovetz

President, Opal Kelly Incorporated



Register Now!

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Vertical spacers are responsive and 50% smaller on mobile than on tablet+.
Click the HTML icon in the toolbar above to edit spacer height.
TO EDIT: Change the class="spacer-3" to any number between 0 (none) and 5 (most) to resize a spacer. Ex. class="spacer-5"
Vertical spacers are responsive and 50% smaller on mobile than on tablet+.